2004   Announcements.       Annual users meeting, 12 January 2005 in Paris [ french - english ]       CMP INTRODUCING CMOS090 PROCESS, July 2004       ESSDERC-ESSCIRC'2005: Circuit Exhibition, July 2004       CMP introducing BCD-SOI PROCESS, June 2004       CMP introducing BICMOS7RF process, March 2004       Annual users meeting, 12 January 2004 in Paris Previous Announcements.       Seminar on MMIC Design Techniques, 23 - 25 June 2003       CMP introducing InP HBT process from VITESSE       Come and see us at DATE 2003, 4-6 March 2003, Munich, Germany       DATE 2003 Conference       Seminar on MMIC Design Techniques on 9, 10, 11 September 2002       DATE 2002 Design Contest       CMP award at DATE 2002       Date 2002 Conference       CMP certified ISO 9002       Annual users meeting; 9 January 2002 in Paris       Seminar on MMIC Design Techniques       CMP introducing HCMOS9 .12µ CMOS       CMP introducing HBT SIGE BICMOS 0.35µ       Annual users meeting; 24 January 2001 in Paris       DATE 2001 Design Contest       MEMS design kit for AMS from MEMScAP       CMP introducing SOI/SOS 0.5µ       CMP Provides ARM® Solutions to Academic Institutions       European Design Automation Roadmap       Annual users meeting; 24 January 2000       CMP introducing .18µ CMOS       MEMScAP Engineering Kits available from CMP

Grenoble, July 2004 - CMP announce the introduction of the CMOS090 90nm CMOS process from STMicroelectronics (Central R&D, Crolles).

This new CMOS090 design platform is based on ST's latest 90 nm CMOS process technology.
The process is intended for System-on-Chip (SoC) and ASIC solutions that target wireless, low-power, networking, and hi-speed applications.
Based on dual-damascene copper technology, it allows 6 to 9 metal layers of interconnect and a library density of more than 400,000 gates per mm².

• 65nm poly length (90nm drawn)
• Dual Vt MOS transistors
• Dual gate oxide
• Dedicated process flavors for high performance or low power
• Dual-damascene copper for interconnect
• 0.28um metallization pitch
• Analog/RF capabilities
• Fully compatible with e-DRAM
• Various power supplies supported : 3.3V, 2.5V, 1.8V, 1.2V, 1V
• Dual standard cell libraries (density/speed), (430kgates/mm²/350 kgates/mm²
• Total of > 1000 core cells
• Gate delay of 11ps (standard Vt)
• Embedded memory SRAM/ROM/DRAM

The design kits are supported under Cadence for full-custom analog/RF: Analog-Artist, Composer, Eldo, Spectre, NCSim, Virtuoso & Layout-XL & ICC. DRC/LVS are supported under Mentor/Calibre. Standard-cells design flows are supported under Synopsys Design-Compiler/Physical Compiler and Cadence/SOC Encounter.

This process is available for prototyping to Education Institutions and Research Labs. The cost is 5,000 euros/mm² (minimum cost = 1 mm²). MPW runs will start in Q4 2004.

CMP is a broker for a number of technologies (prototyping and low volume production). Since 1981, 550 Institutions from 60 countries have been served, through nearly 500 runs, 20 semiconductor houses have been interfaced.

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CIRCUIT EXHIBITION

The European Solid-State Circuits Conference (ESSCIRC) and the European Solid-State Device Research Conference (ESSDERC) '05 will be held in Grenoble - France from 12-16 September 2005. ESSCIRC and ESSDERC have a long, established tradition of high quality conferences dealing with all aspects of solid-state circuits, devices and technologies. This joint meeting is an event of major importance on the European scale. About 1000 conference attendees are expected. A vendor exhibition is also going to be organized.

Details can be found at : www.essderc2005.com or www.esscirc2005.com

A circuit exhibition will also be organized. Three categories of circuits will be considered: Education, Research, Industry. The circuits must have been fabricated by the submission deadline. Plots of the circuits will be exhibited and a catalogue will be edited. The circuit exhibition is sponsored by CMP. Arrangements are being made with other services like CIC in Taiwan, CMC in Canada, ICC in China, IDEC in Korea, MOSIS in USA and VDEC in Japan to ensure a smooth coordination.

For each category, submit the Application Form for circuit exhibition. It includes the information on the circuit, results of testing, the manufacturing date, etc. For circuits manufactured by CIC, CMC, CMP, ICC, IDEC, MOSIS or VDEC please give the run reference.

The submission deadline is 17 June 2005.

Please send your submission to CMP, attn: Hubert DELORI.

For more information contact:

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CMP introducing BCD-SOI Process

San Diego, USA, Design Automation Conference, and Grenoble, France - CMP announce the introduction of the high voltage BCD-on-SOI technology from Atmel®.

This process called SMARTIS, combines bipolar, CMOS and DMOS devices on the same SOI substrate. It enables system-on-chip applications including analog and digital parts, both in high voltage and low voltage, to be in the same chip. A broad range of smart power applications may be implemented with this technology, like automotive, telecommunication, medical, and industrial electronics.
SMARTIS is based on a 20 (22) mask process with 80V breakdown voltage. The low voltage CMOS part allows to reach a gate density comparable to 0.5 µm standard CMOS, while the high voltage part enables a secure power transistor size reduction of more than 30% compared to standard bulk BCD technology.
The electrical features and cross-sections of CMOS, Bipolar, and DMOS devices are as follows:

The design kit is supported under Cadence with full-custom and standard-cells capabilities. It allows accurate mixed signal simulation of digital and analog circuits, layout generation, and circuit verification.
This process is available for prototyping and low volume production to Education institutions, Research Labs, and Industrial Companies.

CMP is a broker for a number of technologies (prototyping and low volume production). Since 1981, 550 Institutions from 60 countries have been served, through nearly 500 runs, 20 semiconductor houses have been interfaced.

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CMP introducing BICMOS7RF process

Grenoble, 5 March 2004 - CMP announce the introduction of the BICMOS7RF HBT SiGe:C BiCMOS 0.25 µ process from STMicroelectronics (Cellular Terminals Division, Grenoble and Central R&D, Crolles).

The process is optimized to address RF needs with high quality and high performance for wireless RF applications. This process represents the next generation of the BICMOS6G 0.35 µ process. The comparison results give for BICMOS7RF better HF noise figure, substrate coupling reduction, power amplifier integration, high performance passive devices, and higher the CMOS density.

BiCMOS6G process specifications 0.25 µ gate length (2.5 V power supply for CMOS) 5 metal layers / thick top metal 2.5 µ Shallow trench isolation for CMOS Deep trench isolation for bipolars Substrate resistance: 50 Ohm.cm NISO for NMOS isolation Low voltage NPN HBT (FT = 55 GHz - BVCEO = 2.8V min) High voltage NPN HBT (FT = 30 GHz typ - BVCEO = 6.0 V typ) Low noise characteristics (NFmin = 0.4 dB at 2 GHz) Isolated Vertical PNP (FT = 6 GHz typ - BCEO = 9.5 V typ) MIM capacitors: 5fF/µm2

The design kits are supported under Cadence for full-custom analog/RF: Analog-Artist, Composer, Eldo, Spectre, ADMS, NCSim, Virtuoso & Layout-XL & ICC.
DRC/LVS are supported under Mentor/Calibre with a ST custom interface into Virtuoso.
Digital Standard-cell design is supported under Synopsys CAD tools: DesignCompiler, Primetime, Apollo,…
This process is available for prototyping to Education institutions, Research Labs, and Industrial Companies.

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Seminar on MMIC Design Techniques

OMMIC will organize a 3 days seminar: "Seminar on MMIC Design Techniques", 23 - 25 June 2003 in Paris.

• See the Program.
• Registration Form, prices and details.

Contact: J.F Paillotin CMP Phone: +33 4 76 57 47 97 E-mail: Jean-Francois.Paillotin@imag.fr

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CMP introducing InP HBT process from VITESSE

Grenoble, France - January 2003 - In cooperation with MOSIS, CMP is introducing foundry services using Indium Phosphide HBT process from VITESSE: VIP-1™.

The VIP-1 process includes high performance SHBT devices with other active and passive devices and multiple levels of metal interconnect. This process has been qualified for production usage and has an expected turnaround time for prototype circuits of 13 weeks, which is more than two times faster than competitive technologies such as SiGe. InP foundry services from VITESSE and MOSIS are available today, with quarterly fabrication runs initially planned.

The VIP-1 process offers circuit designers the benefits of both high-speed and high-voltage operation suitable for digital, analog, and RF circuits at 10Ghz or higher. The process uses four-inch diameter semi-insulating substrates and is designed for high performance and high yield. The key active device is a SHBT, characterized by f_T =150GHz, F_MAX =150GHz (at IC=1mA/µm), and BV_CEO in excess of 4.5V. The process also includes resistors and capacitors, and three layers of metal interconnect. Device models and design rules are supported in the Cadence design environment and the robust process supports junction temperatures of 125°C.

The silicon-like interconnect and volume manufacturing capability developed by VITESSE makes this process technology ideal for many applications requiring the performance or optoelectronic properties of InP such as high-voltage drivers, high-frequency amplifiers, high-speed DACs and ADCs, adaptive RF electronics, automotive radar, low loss waveguides and optical components such as photodetectors. Circuits, including VITESSE's 10Gbps RZ modulator driver, 4:1 MUX and limiting amplifier, that were developed using this process have already been deployed into commercial telecommunications systems.

To demonstrate the abilities of the process, VITESSE produced the industry's most complex InP integrated circuit, a 40Gbps 16:1 MUX with integrated PRBS 2³¹-1 generator, which contains close to 5000 HBTs. VITESSE will continue to advance the uses of InP technology through the development of the next generation process: VIP-2^™, a dual HBT InP process with f_T = 300GHz and BV_CEO in excess of 10V.

About VITESSE.
VITESSE is a leading designer and supplier of innovative, high-performance integrated circuits (ICs) and optical modules used in next generation networking and optical communications equipment. The Company's products address the needs of Enterprise, Access, Metro, Core, and Optical Transport network equipment manufacturers who demand a robust combination of high-speed, high-service delivery and low-power dissipation in their products. In concert with its broad communications product portfolio, VITESSE also develops ICs for storage area networking and enclosure management. VITESSE is headquartered in Camarillo, CA, USA. Company and product information is available by calling 1-800-VITESSE.

About CMP.
CMP is broker for a number of technologies (prototyping and low volume production) including integrated circuits, MEMS and MCMs. Since 1981, more than 540 Institutions from 60 countries have been served. Integrated circuits are available down to .12µ CMOS 6LM, .8µ SiGe HBTÐCMOS DLP/DLM, .35µ SiGe BiCMOS 5LM, .5µ SOI/SOS CMOS, .2µ GaAs HEMT MMIC from STMicroelectronics, austriamicrosystems, OMMIC and Peregrine. Design Kits are provided for most CAD tools. CMP is ISO 9002 certified. CMP is based in Grenoble, France.

About MOSIS.
MOSIS, founded in 1981 and originally funded by DARPA, has moved into commercial, research and consumer markets. Benefiting the most from this prototyping process is the customer. Once prototyping is complete and the design is ready for dedicated fabrication, the customer goes directly to the foundry. The parts, already fabricated and tested in the prototyping stage, are now ready for full production. This streamlined development saves resources and time, accelerating the product's time to market. MOSIS is based in Marina del Rey, CA, USA.

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Seminar on MMIC Design Techniques

OMMIC will organize a 3 days seminar: "Seminar on MMIC Design Techniques" on 9, 10, 11 September 2002 at Limeil Brevannes near Paris.

• See the Program.
• Registration Form, prices and details.

Contact: J.F Paillotin CMP Phone: +33 4 76 57 47 97 E-mail: Jean-Francois.Paillotin@imag.fr

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DATE Design Contest on operational designs

In addition to the Designers' Forum papers that are automatically potential candidates to the DATE Design Contest on Operational Designs, submissions to the contest are still accepted till 31 December 2001. One CMP Design Contest Prize will be awarded and announced during the Plenary Session at DATE 2002, to be held in PARIS, 4-8 March 2001.

This contest, organised by CMP, is designed to promote the research and development at Universities and Research Laboratories world-wide in the domain of System on Chips in very deep sub-micron CMOS technologies, MEMS and other advanced processes (SiGe, SOI/SOS, HEMT GaAs, sub-micron CMOS). The contest addresses operational designs (i.e. designs that have been manufactured and tested).

CMP has introduced a .25µ CMOS 6LM process from STMicroelectronics late 1997 and the .18µ CMOS 6LM has been announced in July 1999. Many designs have been manufactured on these processes. The .12µ CMOS 6LM has been announced in July 2001. A very large number of designs have been also manufactured on the .6µ/.8µ CMOS and BiCMOS processes from AMS. MEMS have been introduced several years ago on various processes (bulk and surface micromachining). IPs like ARM cores are also available to design very complex systems.

Who can participate ?
The contest is open to any students, PhD-students, research groups from any University or public funded research group worldwide.

Contest specifications
The circuit must have been fabricated in a CMP run, and must have been tested. The deadline to submit an entry to the contest is 31 December 2001. The results will be communicated by 31 January 2002. A panel of experts will judge the entries, considering criteria like the originality of the design, the complexity of the design, the test results (mandatory), the potential industrial interest. The format of the report is free, but it should not exceed 10 pages, including figures, diagrams, etc... The winner of the Prize will be required to attend the Plenary Session at DATE to receive the Prize, on 5 March 2002.

The winner will be awarded free prototyping on a CMP run, in the same process as the process in which he submitted his entry (surface depending on that process), a free layout plot, an introduction to potential industry customers.

Bernard COURTOIS CMP - 46, avenue Félix Viallet 38031 GRENOBLE Cedex - France		Tel: +33 4 76 57 48 04 Fax: +33 4 76 47 38 14 E-mail: Bernard Courtois

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Annual users meeting

Grenoble, 5 november 2001.

Dear Madam, dear Sir,

The annual CMP users meeting will take place on Wednesday 9 January 2002 in Paris at:

Maison de la Chimie 28, rue Saint Dominique 75007 PARIS

Room: 101 Tel: +33 1 40 62 27 00 http://www.maisondelachimie.com

The meeting will begin at 10.00 a.m. and will finish at 4.00 p.m. It is open to every person, from academia or research laboratory or private company, using, or interested in, the CMP services. The French language will be mainly used during this meeting. Sandwiches and soft drinks will be available on site. Please register if you plan to attend.

Agenda

General data on 2001 runs and evolution

AMS

ST (0.12 µ CMOS, 0.35 µ BiCMOS SiGe, ...)

PEREGRINE

OMMIC

Microsystems

Packaging

Distribution of libraries and kits

ARM

CAD tools offers

Information on CAD tools provided by CAML for french Universities

Quality assurance

Other developments in 2002 (discussion)

CMP budget

Miscellaneous

Sincerely Yours,

B. COURTOIS
Director CMP Service

Seminar on MMIC Design Techniques

OMMIC will organize a 3 days seminar: "Seminar on MMIC Design Techniques" on 28, 29, 30 January 2002 at Limeil Brevannes (near Paris).

• See the Program.
• Registration Form, prices and details.

Contact: J.F Paillotin CMP Phone: +33 4 76 57 47 97 E-mail: Jean-Francois.Paillotin@imag.fr

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CMP Award at DATE 2002

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CMP introducing .12µ CMOS

Las Vegas, USA and Grenoble, France - CMP announced at the Design Automation Conference and at the Microelectronics Education Workshop the introduction of the HCMOS9 .12µ CMOS process from STMicroelectronics (Crolles, France).

The HCMOS9 process has the following features:

• Gate length: .13µ (drawn), .11µ (effective)
• Triple well
• Power supply 1.2 V
• Multiple Vt transistor offering (Ultra low leakage, Low leakage, High speed)
• Threshold voltages (for 3 families above):
  VTN = 570/500/380 mV,
  VTP = 590/480/390 mV
• Isat (for 3 families above):
  TN @ 1.2 V: 410/535/680 µA/µm
  TP @ 1.2 V: 170/240/320 µA/µm
• 6 metal layers in standard. Up to 8 metal layers in option
• Low k inter-level dielectric

Full custom designs are supported using Virtuoso layout editor and LAS synthesizer. The layout verifications (DRC, ERC, extraction, LVS) are fully supported for Calibre. Transistor-level simulations are supported under Eldo, and Hspice.

Standard-cell designs are supported using Verilog/VHDL descriptions for synthesis and simulation. Synthesis is supported under Synopsys. Simulation is supported under Verilog-XL, Leapfrog, NCSIM and ModelSim. The automatic place & route is supported under Cadence suite of tools.

This process is available for prototyping to Education Institutions and Research Laboratories, on a cooperation basis. No commercial designs are accepted at this early stage. It is expected that later on, the process will be available on a commercial basis for small volume production to Education Institutions, Research Laboratories and specified Companies. A more advanced process would then be made available for Education and Research.

CMP also gave a summary of the achievements to date on the .25µ CMOS (introduced in 1997) and .18µ CMOS, introduced in 1999. A total of 86 projects has been or is being manufactured. Applications addressed by designers are RF circuitry, filters, opto-electronic circuitry, characterization, inductors, analog memories, very complex systems like a neural network (2.7 million transistors in 11 mm² from DTU in Denmark and a processor in 50 mm² from LIP6 in France). Institutions that submitted circuits are from Denmark, Finland, France, Greece, Hong Kong, Japan, Sweden, Switzerland and United Kingdom. More than one hundred Institutions have been provided with the design rules. It is expected that many more projects will go to fab, after the Institutions get acquainted with the design flow on deep-submicron processes.

Also CMP announced that the .18µ CMOS process becomes now available on a more broader basis, in the frame of a deep submicron consulting from CMP (check with CMP for details).

The .25µ CMOS process will be progressively phased out. Several runs will be available in 2001, and fabrication will be lateron be organized upon possibilities available from STMicroelectronics.

SEM cross section view of the .12µ CMOS process
(courtesy of STMicroelectronics).

CMP is a broker for a number of technologies (prototyping and low volume production). Since 1981, 500 Institutions from 60 countries have been served, through more than 300 runs, 20 semiconductor houses have been interfaced.

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CMP introducing HBT SIGE BICMOS 0.35µ

Paris, France - CMP today announced at the CMP Users meeting the introduction of the BiCMOS6G HBT SiGe BiCMOS 0.35µ process from STMicroelectronics (Wireless Division, Grenoble and Central R&D, Crolles).

The process is of high quality, suitable for System on Chip applications, since it is able to handle large high density/high performance digital applications as well as high performance analog and RF applications in the same chip.

BiCMOS6G process specifications

• Complementary bipolar process with vertical isolated PNP
• Single layer poly / 5 layers metal
• Metal 5 is thick 2.5µ Alu
• CapaL option: 1 nF/mm²
• MIM option: 2 nF/mm²
• High resistive poly: 1 kOhm/sq
• NPN 3.3 V (FT = 45 GHz, NF @ 2GHz = 0.8dB)
• NPN 5.0 V (FT = 25 GHz)
• Standard Power supplies: 3.3 V or 5.0 V

This process is available for prototyping to Education Institutions and Research Laboratories, on a cooperation basis. No commercial designs are accepted at this early stage. It is expected that later on, the process will be available on a commercial basis for small volume production to Education Institutions, Research Laboratories and specified Companies.

SEM cross section view of SiGe HBT (Courtesy of STMicroelectronics).

Schematic cross section of SiGe HBT.

CMP is a broker for a number of technologies (prototyping and low volume production). Since 1981, 500 Institutions from 60 countries have been served, through more than 300 runs, 20 semiconductor houses have been interfaced.

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Annual users meeting

Grenoble, 14 november 2000.

Dear Madam, dear Sir,

The annual CMP users meeting will take place on Wednesday 24 January 2001 in Paris at:

Maison de la Chimie 28, rue Saint Dominique 75007 PARIS

Room: 162 Tel: +33 1 40 62 27 00

The meeting will begin at 10.00 a.m. and will finish at 4.00 p.m. It is open to every person, from academia or research laboratory or private company, using, or interested in, the CMP services. The French language will be mainly used during this meeting. Sandwiches and soft drinks will be available on site. Please register if you plan to attend.

Agenda

General data on 2000 runs and evolution

AMS

STM

PML

Microsystems

Small volume production

Packaging

Distribution of libraries and kits

Deep-Submicron success stories

SiGe

0.18 CMOS

SOI / SOS

CMP/ARM offer

Other CAD tools offers

Information by LIRMM on CAD tools provided by CAML for french Universities

Quality assurance

CMP budget

Other developments in 2001 (discussion)

Miscellaneous

Sincerely Yours,

B. COURTOIS
Director CMP Service

DATE Design Contest on operational designs

This contest, organised by CMP, is designed to promote the research and development at Universities and Research Laboratories world-wide in the domain of System on Chips in very deep sub-micron CMOS technologies, MEMS and other advanced processes (SiGe, SOI/SOS, HEMT GaAs, sub-micron CMOS). The contest addresses operational designs (i.e. designs that have been manufactured and tested).

CMP has introduced a .25µ CMOS 6LM process from STMicroelectronics late 1997, and many designs have been already manufactured, the .18µ CMOS 6LM has been announced in July 1999, MEMS have been introduced several years ago on various processes (bulk and surface micromachining), SiGe and SOI/SOS have been more recently introduced, but runs are available in 2000. IPs like ARM cores are also available to design very complex systems.

Who can participate?
The contest is open to any students, PhD-students, research groups from any University or public funded research group worldwide.

Contest specifications
The circuit must have been fabricated in a CMP run, and must have been tested. The deadline to submit an entry to the contest is 31 December 2000. The results will be communicated by 31 January 2001. Committee including experts from Education, Research and Industry will judge the entries, considering criteria like the originality of the design, the complexity of the design, the test results (mandatory), the potential industrial interest. The format of the report is free, but it should not exceed 10 pages, including figures, diagrams, etc. The panel of experts will possibly distinguish several categories of designers, like students and researchers, and possibly distinguish several process categories. The winner of the 1^st Prize will be required to attend the Plenary Session at DATE to receive the Prize, on 14 March 2001.

The winners will be awarded free prototyping on a CMP run, in the same process as the process in which they submitted their entry (surface depending on that process), a free layout plot, an introduction to potential industry customers.

Committee
The Committee is including the following experts:

Pr. Michel DECLERCQ Dr. Andreas KAISER Pr. Hugo DE MAN Dr. Vassilios GEROUSIS Pr. José DA FRANCA Pr. Volker KEMPE Dr. Jo BOREL Dr. Marc ROCCHI		EPFL - Switzerland IEMN - France KUL & IMEC - Belgium Infineon - Germany IST & Chipidea - Portugal AMS - Austria STM - France PML - France
Bernard COURTOIS CMP - 46, avenue Félix Viallet 38031 GRENOBLE Cedex - France		Tel: +33 4 76 57 48 04 Fax: +33 4 76 47 38 14 E-mail: Bernard Courtois

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MEMScAP MEMS Foundry Module for AMS technology available through CMP

Grenoble, France - August 2000 - CMP and MEMScAP S.A. announce the introduction of a MEMS Foundry Module for the 0.8µ CMOS DLP/DLM compatible front side bulk micromachining technology from AMS, Austria.

Started in 1995, the micromachining program of CMP allows Universities, R&D Laboratories and Industry to have easy access to MEMS technologies. Microelectronics-compatible bulk micromachining (in CMOS, BiCMOS and HEMT GaAs) as well as MEMS-specific processes have been provided.

The engineering kit enables front side bulk micromachining process based on the 0.8µ CMOS DLP/DLM technology from AMS. The Foundry Module offers customization for MEMScAP design tool suites available for Mentor Graphics and Cadence flows. MEMScAP software is distributed by CMP.

This Foundry Module offers the following features:

• Technology files and design rule checker, checking the specific MEMS design rules
• 3-D viewer
• Layout to and from 3D Solid Model Generator (link to ANSYS)
• Anisotropic etching simulation
• MEMS Behavioral models library (HDL-A, VHDL-AMS)

About CMP:
CMP is a broker for a number of technologies (prototyping and low volume production). Since 1981, 400 university centers and 130 industrial companies from 60 countries have been served, more than 3000 integrated circuits have been fabricated and 20 semiconductor houses have been interfaced.

MEMScAP customers include 3M, Robert Bosch, Canadian Microelectronics Corporation, Cleveland Clinic Foundation, Cronos/MCNC, Eastman Kodak, Ford Motor Company, Fujitsu Laboratories, Lucent Technologies, NASA, Schlumberger, Microsoft, Motorola, National Instruments, Procter & Gamble, Rockwell, Sensonor, University of Tokyo and Xerox Corporation. European headquarters are located in Grenoble, France. North American headquarters are in Raleigh, North Carolina. MEMScAP also has a growing operations center in Berlin, Germany. Sales offices and distributors are located around the world. More information on the company's products and services can be obtained at MEMScAP

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CMP certified ISO 9002

About CMP:
CMP is broker for a number of technologies (prototyping and low volume production). Since 1981, more than 500 Institutions from 60 countries have been served, through more than 300 manufacturing runs, 20 semiconductor houses have been interfaced. Integrated circuits are available on CMOS down to .18µ, BiCMOS (.8µ), SiGe (.8µ), SOI/SOS CMOS (.5µ), MMIC GaAs (HEMT .2µ). MEMS are manufactured on compatible front-side bulk micromachining (CMOS, BiCMOS, GaAs) and surface micromachining. MCMs L, C, D and V are available. Design Kits are provided for most CAD tools.

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CMP introducing SOI/SOS 0.5µ from Peregrine Semiconductor

In cooperation with MOSIS, CMP is introducing the SOI/SOS 0.5um process (UTSi CMOS process) from Peregrine Semiconductor, USA.

Peregrine UTSI SOI/SOS process is based on Silicon-On-Sapphire substrate. The process supports digital densities of up to 400k gates at 0.4µW/MHz/gate, with Fmax greater than 50 GHz and NFmin less than 0.8 dB. Sapphire is non-conducting and does not absorb, attenuate, distort or combine RF signals. In RF applications, SOI/SOS offers the benefits of this insulating substrate, providing high quality factor passive RF parts required in wireless applications. Passive elements can be inductors, capacitors or resistors. The isolating substrate also increases performances by reducing switch capacitances thus providing high frequency operation, low power consumption and low voltage operation. Finally this SOI/SOS process offers excellent radiation tolerance thus allowing space and harsh environment applications.

Some process features are:
        * Active silicon substrate thickness: 1200 Å
        * Gate length: 0.5µ
        * Double layer polysilicon, allowing accurate POLY1/POLY2 capacitors
        * Triple layer metal
        * Power supply: 3.3 Volt
        * Threshold voltages are 0V, (-)0.35V, (-)0.8V for NMOS (PMOS) depending on MOS types

In summary the advantages of SOI/SOS in terms of:
        * Low power / low voltage
        * High Q passive RF components
        * Radiation tolerant operations
        * Integration and reliability
make this technology particularly suitable for wireless communications, systems on a chip, RF and microwave, space and harsh environment applications.

The price is 1300 Euros per square millimeter for 25 pieces. A design kit for CADENCE is available for free. The first runs will take place in May and September 2000.

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CMP Provides ARM® Solutions to Academic Institutions

Grenoble, France and Cambridge, UK - February 15, 2000.
Circuits Multi-Projets (CMP) and ARM [(LSE:ARM); (Nasdaq:ARMHY)] today announced they have finalized an agreement which enables CMP to provide academic institutions with a complete solution for developing ARM® core-based system-on-chip (SoC) devices. This program, which is being driven by the industry's growing demand for SoC expertise, will provide universities worldwide with access to ARM core-based silicon and development tools, enabling engineering students to gain the skills and experience necessary to develop sophisticated integrated circuits and systems.

"As the system-on-chip trend continues to gain momentum, additional requirements and expertise will be expected of system developers and IC designers," said Eric Lalardie, business development manager, ARM. "By providing ARM's industry-leading SoC technologies to engineering students worldwide, we are able to help develop the expertise and experience that will shape the engineers of tomorrow."

CMP is a technology broker, providing academic institutions with the products and support necessary to equip a university training program or research and development (R&D) facility. Through this program, the company will provide the ARM Developer Suite (ADS Unix and PC versions), a range of ARM Evaluation Boards (AEBs) and the Multi-ICE® debug unit. CMP will also provide sample silicon from key ARM Silicon Partners.

"As deep submicron processes rapidly lead to system-on-chip solutions, microelectronics engineers are rapidly becoming system developers, mastering hardware-software implementation for novel silicon architecture," said B. Courtois, director, CMP. "With this agreement with ARM, CMP will be well placed to supply academic institutions worldwide with products which will greatly help future engineers to gain these necessary competences.".

ARM also works directly with universities, including Manchester University (UK), University of California at Berkeley (US), Université Catholique de Louvain (Belgium) and Aachen University (Germany), to promote ARM core-related research. Through this agreement with CMP, ARM will be better able to support its expanding University Program.

CMP will provide ARM development solutions and silicon to publicly funded academic institutions for educational and research purposes. For more information on this program, contact CMP at
Tel: +33 476574804,
Fax: +33 476473814

About ARM

ARM, a leading intellectual property (IP) provider, licenses high-performance, low-cost, power-efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM's microprocessor cores are rapidly becoming the volume RISC standard in such markets as portable communications, hand-held computing, multimedia digital consumer and embedded solutions.

ARM, ARM Powered, Thumb and StrongARM are registered trademarks of ARM Limited. Multi-ICE is a trademark of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holdings plc (LSE: ARM and NASDAQ: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM, INC.; ARM KK; ARM Korea Ltd.

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Annual users meeting

Grenoble October 1999

Dear Madam, dear Sir,

The annual CMP users meeting will take place on Monday 24 January 2000 in Paris at:

Maison de la Chimie 28, rue Saint Dominique 75007 PARIS

Room: 162 Tel: +33 1 40 62 27 00

The meeting will begin at 10.00 a.m. and will finish at 4.00 p.m. It is open to every person, from academia or industry, using, or interested in, the CMP services. The French language will be mainly used during this meeting. Sandwiches and soft drinks will be available on site. Please register if you plan to attend.

Agenda

General data on 1999 runs and evolution

AMS

STM

PML

Microsystems

Small volume production

Packaging

Distribution of libraries and kits

Design-flow for advanced CMOS

SiGe

0.18 CMOS

SOI / SOS

CMP/ARM offer

Other CAD tools offers

Information by LIRMM on CAD tools provided by CAML for french Universities

Quality assurance

CMP budget

Other developments in 2000 (discussion)

Miscellaneous

Sincerely Yours, B. COURTOIS
Director CMP Service

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CMP introducing .18µ CMOS

Washington, USA and Grenoble, France - July 19, 1999 - CMP today announced at the Microelectronics Education Workshop the introduction of the HCMOS8 .18µ CMOS process from STMicroelectronics (Crolles, France).

The HCMOS8 process has the following features:

• Gate length: .18µ (drawn), .15µ (effective)
• Triple well
• Power supply 1.8 V
• Threshold voltages: VTN = 420 mV,
          VTP = 400 mV
• Isat: TN @ 1.8 V: 600 µA/µm
          TP @ 1.8 V: 280 µA/µm
• 6 metal layers + local interconnect
• Low k inter-level dielectric

Low leakage / low power and 3.3 V power supply options are also available.

Design kits are supported under Cadence, Synopsys, Eldo and Hspice.

Full custom designs are supported using Virtuoso layout editor and LAS synthesizer. The layout verifications (DRC, ERC, extraction, LVS) are fully supported for Diva and Calibre. Transistor-level simulations are supported under Eldo level 59, and Hspice level 50.

Standard-cell designs are supported using Verilog/VHDL descriptions for synthesis and simulation. Synthesis is supported under Synopsys. Simulation is supported under Verilog-XL, Leapfrog and VSS. The automatic place & route is supported under Silicon Ensemble suite of tools.

This process is available for prototyping to Education Institutions and Research Laboratories, on a cooperation basis. No commercial designs are accepted at this early stage. It is expected that later on, the process will be available on a commercial basis for small volume production to Education Institutions, Research Laboratories and specified Companies. A .15µ process would then be made available for Education and Research.

CMP also gave a summary of the achievements to date on the .25µ CMOS process introduced late 1997. A total of 28 projects have been or are being manufactured. Applications addressed by designers are RF circuitry, filters, opto-electronic circuitry, characterization, inductors, analog memories, very complex systems like a neural network (2.7 million transistors in 11 mm² from Helsinki University of Technology in Finland and a processor in 50 mm² from LIP6 in France). Institutions that submitted circuits are from Denmark, Finland, France, Japan, Sweden, Switzerland. A total of 80 Institutions have been provided with the design rules. It is expected that many more projects will go to fab, after the Institutions get acquainted with the design flow on deep-submicron, very different from a micronic or submicronic process.

Also CMP announced that the .25µ CMOS process becomes now available on a more broader basis, in the frame of a deep submicron consulting from CMP (check with CMP for details).

Finally, CMP announced that an option on the .25µ will be available in Q4 1999: the metal/metal capacitors option. Such an option will allow excellent performances for RF designs.

CMP is a broker for a number of technologies (prototyping and low volume production). Since 1981, 450 Institutions from 40 countries have been served, through more than 300 runs, 20 semiconductor houses have been interfaced.

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MEMScAP Engineering Kits available from CMP

VULCAIN®, the Generic MEMS Engineering Kit is a customizable design kit (it includes a customization procedure to any process technology), it runs in conjunction with Mentor Graphics and provides the following features:

• MEMS oriented schematic capture
• a set of parameterized cells described at different levels (symbolic, behavioral, layout)
• optimization tools (Opsim) useful for model development as well as specification parameter recycling
• HDL-A code generator of non-linear behavioral models from lower level description
• full verification of the design functionality (Continuum/Eldo/HDL-A)
• layout generators for mechanical structures, such as elementary structures (i.e. bridges, cantilevers, membranes, etc.) and application oriented structures coupled to
• the behavioral models, allowing the schematic driven layout feature
• the layout generation of the whole MEMS (electronic and non-electronic parts) and a design rule verification
• an extended design rule checker which can handle monolithic as well as hybrid designs
• a multi-segment, multi-direction cross-section viewer
• an anisotropic etching simulator for silicon and gallium arsenide as well as a sacrificial layer etching simulator
• layout to 3D-solid model generator
• links to FEM/BEM tools (ANSYS)

KANAGA®, The MCNC/CRONOS Engineering Kit includes in addition to the VULCAIN® Engineering Kit a set of foundry specific modules targeting the MCNC/CRONOS process available from CMP. These modules are a DRC for the MCNC/CRONOS process and a component library. The library includes a fully characterized set of MEMS components (sensors, actuators, building blocks, test structures). Each component comes with a representation at the schematic level, at the system level (behavioral model) and at the layout level. The kit runs in conjunction with Mentor Graphics.

The kit includes:

• all features of VULCAIN® customized to the MCNC/Cronos manufacturing processes
• library components, including:

Active elements motors (electrostatic, thermal) actuators (electrostatic, thermal) resonators sensors

Passive elements electrical mechanical (plates, transmission, springs, sliders, hinges) optical test elements

PRICES:

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Tel: +33 4 76 57 48 04 Fax: +33 4 76 47 38 14 E-mail: CMP

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Tous droits réservés.