|Title||Clock-less AES crypto-Processor (Advanced Encryption Standard)|
|Institution||Concurrent Integrated Systems (C.I.S) Group at TIMA laboratory France – SGDN / DCSSI|
|Run||S12C4-6, STMicroelectronics 0.12 CMOS HCMOS9, chip: AESPLOTS, area: 2.2 mm2|
Clock-less AES Crypto-processor layout
|This circuit implements a Clock-Less AES crypto-processor architecture, compliant with the NIST standard: 128 bit data blocks and 128, 192 or 256 bit keys. The AES chip implements a standard bus interface enabling an easy connection to any synchronous microprocessors or Asics. The circuit, powered at 1.2 volt, ciphers a 128 bit date using a 128 bit key in 1 µs which corresponds to a ciphering rate of 128 Mbit per second.
Due to the robustness of the clock-less Quasi Delay Insensitive logic used to design the chip, the circuit is functional within a wide voltage range, from 1.2 Volt down to 0.4 Volt. This feature is particularly interesting in secure and low-power applications.
|Further information:||Marc RENAUDIN
|© 2013 CMP
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