ams 0.35 Wafer-level bumping

ams Wafer-level packaging ams 0.35 Wafer-level bumping option

TECHNOLOGY CHARACTERISTICS :

Bumps form an evenly distributed array over the whole chip surface.
Electrical connections to CMOS pads with a RDL layer.
I/O Pitch compatible with traditional PCB assembly processes.
Available as an option on all 0.35 MPW runs.

APPLICATION AREA :

Single die flip-chip packaging

DESIGN KIT VERSION :

Option supported by ams hitkit