IC 0.18µm aH18A6

IC ams 0.18µm CMOS High Voltage 6 ML aH18A6

TECHNOLOGY CHARACTERISTICS :

Met. layer(s): 6 metal layers / Thick Metal 6 MiM Capacitors Maximum die size: 2cm x 2cm Standard cells: digital standard cells and IO pads analog standard cells and IO pads Available I/O: I/O cell library with available for 1.8V/5V. High Voltage IO pads for 20V or 50V Temp. range: -40° C. / +180° C. Supply voltage: 1.8V, 5.0V, 20V, 50V (max gate voltage 20V) HV Digital standard cells and IO Libraries: CORELIB_HV: CORELIB for high voltage. IOLIB_HV : High Voltage digital IO pads library.

SPECIAL FEATURES :

High performance analog/digital/High-Voltage applications ?

APPLICATION AREA :

Mixed signal analog digital, HV designs, system on chip

DESIGN KIT VERSION :

4.14

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre, Hspice, Ultrasim, NC-Sim, ams-Designer (Cadence) Eldo, ModelSim, QuestaSim (Mentor Graphics) Hspice (Synopsys)

Verification tools :

Assura, PVS (Cadence) Calibre (Mentor Graphics)

Parasitics extraction tools :

QRC (Cadence) Calibre xRC (Mentor Graphics)

Place route tools :

Encounter Digital Implementation (EDI) (Cadence)

LIBRARIES :

LV Digital standard cells and IO Libraries: - CORELIB: General purpose digital library - CORELIB_3B: Same as CORELIB with 3 busses (VDD, VSS, GND) - IOLIB: IO pads (input, output, bidir). 3.3V and 5V available - IOLIBC_3B: Core limited digital IO Libraries - Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. Analog standard cells Libraries: - IOLIB_ANA: Analog IO pads library - IOLIBC_ANA_3B: Core limited Analog IO pads library - IOLIB_ANA_HV: High Voltage Analog IO pads library - A_CELLS: Analog Library HV Digital standard cells and IO Libraries: - CORELIB_HV : CORELIB for high voltage. - IOLIB_HV : High Voltage digital IO pads library

TURNAROUND TIME :

Typical: 14-16 weeks (from GDS2 tape to packaged parts)