IC 130nm BiCMOS9MW

IC STMicroelectronics 130nm BiCMOS SiGe 6 ML BiCMOS9MW

TECHNOLOGY CHARACTERISTICS :

CMOS Gate length: 130nm (drawn), 130nm (effective)
Triple well
Power supply 1.2V
Multiple Vt transistor offering (Low Leakage , High Speed)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic;
TP @ 1.2V: 240/310uA/mic
Bipolar SiGe transistors: High Speed NPN, Medium VoltageNPN
Typical beta (for 2 families above): 1000/1000
Typical Ft (for 2 families above): 230/150GHz
6 metal layers in standard
Low k inter-level dielectric
MIM capacitances
2.5V-transistors option is also available.

DESIGN KIT VERSION :

2.9.b

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS GoldenGate (Keysight)

Verification tools :

Calibre (Mentor Graphics) PVS (Cadence)

Parasitics extraction tools :

StarRCXT (Synopsys), QRC (Cadence)

Place route tools :

Innovus (Cadence), ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells and the same. On request: - DP: Datapath leaf cells libraries - HD: High density core libraries IO cells Libraries: - 1.8V, 2.5V, 3.3V IO pads: - 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog - Staggered IO pads - Flip-Chip pads - Level Shifters, and compensation cells On request: - LVDS Pads - DLL, PLL - …

TURNAROUND TIME :

Typical leadtime: 16-18 weeks from MPW run deadline to packaged parts