IC 130nm HCMOS9A

IC STMicroelectronics 130nm CMOS High Voltage 4 ML HCMOS9A

TECHNOLOGY CHARACTERISTICS :

Gate lenght: 130nm (drawn), 130nm (effective)
Triple Well Power supply: 1. 2V for Digital, 4.6V for Analog application Multiple
Vt transistor offering (Low Power, Analog)
Threshold voltages (for 2 families above): VTN = 700/697mV, VTP = 590/626mV
Isat (for 2 families above): TN: 280/658uA/um
TP: 104/333uA/um 4 metal layers in standard Fluorinated SiO2 Inter Metal dielectrics Bipolar Transistors NPN
Typical beta: 90 Ft Max @ Vbc=0: 2,4GHz 2 specific implant levels: NDRIFT & PDRIFT MIM 5fF/µm2 capacitor
Double gate oxide for analog features.

DESIGN KIT VERSION :

10.7

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)

Verification tools :

Calibre (Mentor Graphics) PVS (Cadence)

Parasitics extraction tools :

StarRCXT (Synopsys), QRC (Cadence)

Place route tools :

ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells and the same. On request: - DP: Datapath leaf cells libraries - HD: High density core libraries IO cells Libraries: - 1.8V, 2.5V, 3.3V IO pads: - 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog - Staggered IO pads - Flip-Chip pads - Level Shifters, and compensation cells On request: - LVDS Pads - DLL, PLL - …

TURNAROUND TIME :

16-18 weeks (from GDS2 tape to packaged parts)