IC 130nm HCMOS9GP

IC STMicroelectronics 130nm CMOS 6 ML HCMOS9GP

TECHNOLOGY CHARACTERISTICS :

CMOS gate length: 130nm drawn poly length
Deep Nwell and Deep Trench Isolation
Power supply 1.2V
Double Vt transistor offering (Low Leakage , High Speed)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic
TP @ 1.2V: 240/310uA/mic
Dual gate oxide (1.2V for core and 2.5V for IO)
Temperature range: -40°C to 175°C
6 Cu metal layers for interconnect
Low k inter-level dielectric
MIM capacitors
Standard cell libraries (more than 180kgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM).

DESIGN KIT VERSION :

9.2

Frontend Backend tools :

Cadence IC 5.1.41_USR6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)

Verification tools :

Calibre (Mentor Graphics)

Parasitics extraction tools :

StarRCXT (Synopsys)

Place route tools :

EDI (Cadence), ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells + IO cells Libraries: - 1.2V, 1.8V, 2.5V, 3.3V, Digital and Analog - Staggered IO pads – bonding pads and fip-chip pads – no compensation cell. On request: - Level Shifters - DP: Datapath leaf cells libraries - HD: High density core libraries - LVDS Pads - DLL, PLL - …

TURNAROUND TIME :

Typical leadtime: 16-18 weeks from MPW run deadline to packaged parts