IC 130nm HCMOS9GP

IC STMicroelectronics 130nm CMOS 6 ML HCMOS9GP

TECHNOLOGY CHARACTERISTICS :

Gate length: 130nm Triple well
Power supply 1.2V
Multiple Vt transistor offering (Low Leakage , High Speed)
Threshold voltages (for 2 families above): VTN = 450/340mV, VTP = 395/300mV
Isat (for 2 families above): TN @ 1.2V: 535/670uA/mic;
TP @ 1.2V: 240/310uA/mic
6 metal layers in standard
Low k inter-level dielectric
MIM capacitances
2.5V-transistors option is also available
WARNING: the 3.3V-transistors option and the Ultra Low Leakage option are no longer available.

DESIGN KIT VERSION :

9.2

Frontend Backend tools :

Cadence IC 5.1.41_USR6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys)

Verification tools :

Calibre (Mentor Graphics)

Parasitics extraction tools :

StarRCXT (Synopsys)

Place route tools :

EDI (Cadence), ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells and the same. On request: - DP: Datapath leaf cells libraries - HD: High density core libraries IO cells Libraries: - 1.8V, 2.5V, 3.3V IO pads: - 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog - Staggered IO pads - Flip-Chip pads - Level Shifters, and compensation cells On request: - LVDS Pads - DLL, PLL - …

TURNAROUND TIME :

16-18 weeks (from GDS2 tape to packaged parts)