IC 55nm BiCMOS055

IC STMicroelectronics 55nm BiCMOS SiGe 8 ML BiCMOS055

TECHNOLOGY CHARACTERISTICS :

CMOS Gate length: 55nm drawn poly length
Deep Nwell and Deep Trench Isolation.
Dual Core Oxide (for 1.2V and for 2.5V)
Power supplies 1.2V and 2.5V for core and IO. 2.5V
Drift NMOS and PMOS.
Dual or triple Vt
Low Power and General Purpose MOS transistor offering.
8 layers Cu metal stack.
Ultra Thick Cu Top Metal (2.8 micron)
Bipolar SiGe-C NPN transistors: High Speed NPN with Ft=320GHz
Medium Voltage NPN with Ft=180GHz, and High Voltage NPN.
Low k inter-level dielectric
MiM capacitors & Fringe MoM capacitors.
Millimiter-wave inductor

DESIGN KIT VERSION :

2.4

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), GoldenGate (Keysight)

Verification tools :

Calibre (Mentor Graphics) PVS (Cadence)

Parasitics extraction tools :

StarRCXT (Synopsys), QRC (Cadence)

Place route tools :

Innovus (Cadence), ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells and the same. On request: - DP: Datapath leaf cells libraries - HD: High density core libraries IO cells Libraries: - 1.8V, 2.5V, 3.3V IO pads: - 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog - Staggered IO pads - Flip-Chip pads - Level Shifters, and compensation cells On request: - LVDS Pads - DLL, PLL - …

TURNAROUND TIME :

24-28 weeks (from GDS2 tape to packaged parts)