IC 65nm CMOS065

IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065

TECHNOLOGY CHARACTERISTICS :

CMOS gate length: 65nm drawn poly length
Deep Nwell and Deep Trench Isolation
Triple Vt MOS transistors (LVT, RVT and SVT)
Low Power and General Purpose MOS transistors
Dual gate oxide (1.0V for core and 2.5V for IO)
Dedicated process flavors for high performance and for low power
Temperature range: -40°C to 175°C
Dual-damascene copper for interconnect, low-k dielectric
7 Cu metal layers for interconnect
Low k inter-level dielectric
MiM capacitors & Fringe MoM capacitors
Inductors
Analog / RF capabilities
Various power supplies supported: 2.5V, 1.2V, 1V
Standard cell libraries (more than 800kgates/mm2)
Embedded memory (Single port RAM / ROM / Dual Port RAM).

DESIGN KIT VERSION :

5.4

Frontend Backend tools :

Cadence IC 6.1.6

Simulation tools :

Spectre (Cadence), Eldo (Mentor Graphics), Hspice (Synopsys), ADS Momentum (Keysight), GoldenGate (Keysight)

Verification tools :

Calibre (Mentor Graphics)

Parasitics extraction tools :

Calibre xRC (Mentor Graphics), QRC(Cadence)

Place route tools :

Innovus (Cadence), ICC (Synopsys)

LIBRARIES :

CORE cells Libraries: - CORE: General purpose core libraries - CORX: Complementary core libraries (complex gates) - CORI: isolation cells – CORL: core libraries for low power applications - CLOCK: Buffer cells and the same for clock tree synthesis - PR: Place and route filler cells + IO cells Libraries: - 1.2V, 1.8V, 2.5V, 3.3V, Digital and Analog - Staggered IO pads – bonding pads and Flip-Chip pads + On request: - Level Shifters - DP: Datapath leaf cells libraries - HD: High density core libraries - compensation cells - LVDS Pads - DLL, PLL - …

TURNAROUND TIME :

Typical leadtime: 22-26 weeks from MPW run deadline to packaged parts