OPEN 3D Backside post-process (TSV, RDL & Bumps)

OPEN 3D IRT Nanoelec/LETI-CEA 0.35µm, 55, 65 & 130 Wafer-level packaging Backside post-process (TSV, RDL & Bumps)

TECHNOLOGY CHARACTERISTICS :

For projects and wafers processed through CMP. Guaranteed minimum delivered pieces: 40. Compatible MPW run combined with MPW Open 3D post-process
Compatible MPW Runs are:
ams C35B4M3, ST CMOS065, ST BiCMOS9MW, ST BiCMOS055.

APPLICATION AREA :

Single die flip-chip, Si-Si assembly

DESIGN KIT VERSION :

CMP/IRT Nanoelec/LETI-CEA 3D Kit

Verification tools :

DRC calibre die-level; DRC calibre 3Dstack assembly-level

LIBRARIES :

3D modules Library