OPEN 3D Frontside Bumps post-process

OPEN 3D IRT Nanoelec/LETI-CEA Wafer-level packaging Flip-Chip Packaging Frontside Bumps post-process

TECHNOLOGY CHARACTERISTICS :

PNG - 332 kb Bumps are manufactured on wafer frontside as a post-process within CEA LETI cleanroom. This interconnection is composed of a pillar of copper upon which a Sn/Ag alloy is deposited to ensure electrical contact. This technique pitch down to 120 µm and offers improved electro migration performances compared to solder bumps.

The process is the following: Seed Layer (or UBM) deposition, Copper electro-deposition (requires masking), Sn/Ag alloy deposition, Seed layer etching and reflow.

This post-process is available for projects and wafers processed through CMP. Guaranteed minimum delivered pieces: 40.

OPEN 3D Bumps post-process option is available for dedicated run only. Diameter/height pair is not imposed and can be chosen within process window. Compatible technologies are: ams C35B4M3, ST CMOS065, ST CMOS028, ST BiCMOS9MW, ST BiCMOS055.

OPEN 3D post-process must be anticipated at an early stage of the project as they require an additional NDA, the distribution a specific DRM and an add-on to the Design-Kit. You must indicate it in the reservation form.

APPLICATION AREA :

Single die flip-chip, 3D/2.5D integration

DESIGN KIT VERSION :

CMP/LETI 3D add-on is required to design post-processed modules. Please refer to the data sheet for more information.

Verification tools :

DRC calibre die-level; DRC calibre 3Dstack for assembly-level checks (at CMP only)

LIBRARIES :

3D modules Library