A 65nm fully differential switched-capacitor integrator

Run reference : S65C15_2 - IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065 (datasheet)

S65C15_2 integrator

The design uses the standard CMOS 65nm process from STMicroelectronics. This circuit generates a ramp stimulus with a step size of 100µV generated thanks to an input capacitor difference. This design is aimed at the static built-in test of high-resolution ADCs. The ramp slope sign can be digitally controlled for each output cycle. The only analog input of the circuit is a fixed DC reference.