Iterative Analogue Encoded Neural Network

Run reference : S65C15_3 - IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065 (datasheet)

S65C15_3 Chip_ENN_MONO

The basic neuron circuit and organisation of the encoded neural networks are described in [1].This circuit integrates a single cluster of 128 analogue neurones having each 30 synapses. The goal is to reduce circuit complexity by iterating on this single cluster to build networks having thousands of neurons. Parallelising chips will further increase this network size.