Low jitter low spurs all digital phase locked loop

Run reference : S65C15_2 - IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065 (datasheet)

S65C15_2 top_padframe

This is a full design of digital phase locked loop based digital to time converter and single phase detector. This design introduces digital techniques working in background to achieve high performance in terms of phase noise and spurs for advanced LTE communication