The testchip contains four low-power designs:
(a) two voltage reference circuits based on different techniques to control the main characteristics, such as the temperature coefficient (TC), power consumption, mismatch caused by the manufacturing process, area, and output noise;
(b) a digital block that incorporates low-pass and high-pass FIR filters;
(c) a fully-differential (current in, voltage out), single-phase, analog lock-in amplifier, as well as instances of the lock-in amplifier subblocks for debugging purpose (low-pass filter, transimpedance amplifier, mixer and operational amplifier); this prototype was designed for a fiber optic sensor application. The chip is carried out in a 180nm CMOS process.