PAnDA F nf

Run reference : S65C15_1 - IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065 (datasheet)

S65C15_1 PAnDA_FUNF

PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability/fault tolerance. PAnDA F nf is fifth and final prototype chip fabricated on the EPSRC funded PAnDA project. The aim of the chip is to test a large, scaled-up version of the complete PAnDA architecture, including elements from all the previous PAnDA prototypes.