PAnDA Vier

Run reference : S65C15_1 - IC STMicroelectronics 65nm Advanced CMOS 7 ML CMOS065 (datasheet)


PAnDA (Programmable Analogue and Digital Array) is a novel FPGA architecture that can be reconfigured at the transistor level, in addition to the digital level. This allows fine-grained, post-fabrication optimisation of mapped designs in order to manipulate the operating-point of the design, mitigate the effects of process variations and improve reliability/fault tolerance. PAnDA Vier is the forth prototype chip fabricated on the EPSRC funded PAnDA project. The aim of the chip is to test a complete version of the PAnDA architecture, including alternative matched widths for the configurable transistors.