A BTI-AWARE SRAM

Run reference : S28I15_1 - IC STMicroelectronics 28nm Advanced CMOS FDSOI 8 ML CMOS28FDSOI (datasheet)

S28I15_1 TonyY15P1

The design is for a BTI-Aware SRAM. A write wordline (WWL) voltage level control scheme is design to lower the WWL voltage before the half-selected cell stability fail due to BTI degradation. The beneficial of the scheme is it recovers the degraded cell stability without changing any SRAM‚s initial operating parameters.