Products distribution

1. How to access the design kits ?

The first step is to fill in the on-line design kit request form
In case of NDA renewal, please notice it in the last section.

Then, if your institution has already a valid NDA/CLA for the requested technology, you will received the latest version of the design kit otherwise you will receive NDA/CLA to sign and return to CMP.

Note that for some advanced technologies, additional forms have to be completed such as the VLAN security form.
The staff member using design kit for ST advanced technologies can be updated. For this you have to send a new VLAN security form with the updated list of staff member.

When all agreements and other document mandatory to access Design Kit through CMP are approved, CMP sends the procedure to download design and updates customers with DRM.

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2. How long to wait for the NDA/CLA ?

NDA/CLA and next the Design Kit/Documentation, are sent by about one month.

3. How to be be informed of a PDK release ?

When a new PDK version is ready to be distributed, a notification is sent to all institutions which have a valid NDA.
The procedure to download and install the PDK release is detailed in the notification.

4. Are there RAM or ROM blocks available for my design ?

The design platform we distribute doesn’t contain any memory cells or compilers (only digital standard-cells and IO cells). But CMP can generate and provide some memory blocks.

For fabrication in a CMP run there is no cost associated to access to these IPs. Generation is getting between one and 2 weeks.

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5. Are there specific IPs available for my design ?

Specific IPs are requested on a case by case basis to STMicroelectronics. They are often not available for outside ST. 

Access might be given if ST knows the type of project that requires specific IPs: applications, technical characteristics... That’s why, in order to make the request CMP need to get from you some slide presentation (5 to 10 slides) describing your project.

This will be reviewed by our contacts at ST who decides if these IPs could be released or not.

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Design Kits installation

6. FTP issues during the downloading ?

You need to be in passive mode on the Linux FTP session. You can toggle from the active to the passive mode by entering the FTP command: “passive”.

Also take care to type: “binary” after your FTP connection to change to the binary mode during the download.

Please note that the files are not visible by the FTP commands "dir" or "ls".

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7. The checksum generated are not the same as given in the readme file ?

If the checksum of the downloaded files are not the same as described in the readme file distributed with the design kit, you may have encountered an issue during decryption. You should retry the DK installation.

Also take care to type: “binary” after your FTP connection to change to the binary mode of the download.

8. Which operating systems are supported ?

The installation procedure is for Linux Red Hat Enterprise 5 or 6. This is the ones officially supported.

If you don’t have this Linux distribution, you can also use CentOS 5.10.

Most of the PDKs are supporting the same Linux distribution and releases as Cadence IC.

You can see the following table showing this.

9. Which shell: bash, csh, tsch…?

The shell used by the different scripts in the design-kits is "tcsh". Bash is not supported.

It is very easy to switch to "tcsh" with CentOS:

Login as root
Go to System -> Administration -> Users and Group

Click on the user you want to change the properties

Click on Properties

A window opens. Change the shell in the item "Login Shell"

Login Shell = /bin/tcsh

10. How to declare my license servers ?

You need to identify the different installation paths of the CAD tools. Then, just replace the paths by the ones provided as an example.

All the examples given in the .cshrc are starting with: /cad

You need also to check the license socket numbers used by the license tool of each of these tools, and build then the LM_LISENCE_FILE variable.

Ex: setenv LM_LICENSE_FILE $LM_LICENSE_FILE:1718@cimekey1:1717@v212 where "1718" and "1717" are the port used and "cimekey1 and "v212" are license server’s names. The character ":" has to be used as a separator, and without space.

The system administrator at your University should be able to help you on site. 

These modifications are quite straightforward.

Design Kit documentations

11. Standard libraries documentation 

There is a documentation for each standard library, available in the PDK.

In the older PDK versions, you can read them through Unidoc tool (after sourcing the .cshrc file from your working directory, enter the following command on the terminal: unidoc &).

Unfortunately, ST is no more supporting Unidoc with newest PDK versions. 
You have to "manually" read the pdf documentations: there are available through _TECHNO_DIR_/_lib_name_/doc/.

Or, open in a browser the HTML files: _TECHNO_DIR_/_lib_name_/doc/html/index.html: it summarizes the documents. You can browse the documentation from there.

12. What is the DRM ?

The Design Rule Manual (DRM) is a document which contains process details (such as cad layers definition...) and all the rules checked during DRC. This document is specific for each technology and confidential. 

When signing NDA with CMP, you should receive, in a secured pdf file, the DRM corresponding to your technology. 

Please note that this pdf file can be read with the software CopySafe PDF Reader under Windows. This is available available for free.

In case of new DRM request in order to replace an old DRM version, please send an official letter with your institution header, stating that you have destroyed the old DRM.

NB: The ISDA/IBM design rules manual contains all the basic rules of the 28nm technology. 
The ST DRM completes or corrects the rules corresponding to the CMOS28FDSOI technology from ST.

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STMicroelectronics MPW runs

13. What files should users provide to reserve area for their design in the coming run ?

After submitted the reservation form, you have to complete your order by filling in the Order form for ICs manufacturing: of-cmp_Oct-16.
Please scan it and send us the document.

Once we receive your order form, we send you a FTP account with password for the transfer of your GDSII file.

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14. When are users supposed to send the reservation forms ?

The reservation one month before the deadline is mandatory. 

After requested it to CMP, please fill in the reservation request form.

Then, to complete your order, please fill in too the Order form for ICs manufacturing: of-cmp_Oct-16.
NB: The circuits are charged only when manufactured.

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15. Which files should be sent for a design submission ?

For each transfer, designers have to send 3 files to CMP, with exactly these names:

  • topcellname.gds.gz: design layout at compressed GDSII format.
  • topcellname.pipo: stream‐out report file generated by the Cadence IC during the GDSII export.
  • topcellname.info: a text file with data about the circuit and a technical contact.

NB: Before sending the files, designers have to run DRCs on the GDSII file and check if they are all correct. Low-density rules should be corrected by tiling generated at CMP (excepted under exclusion areas).

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16. How to export a design at GDSII format ?

  1. On Virtuoso, open the layout view where the top cell of your design is implemented.
  2. In CIW window, select: File > Export > Stream...:
  3. The StreamOut window opens. Some fields are automatically filled, according to your layout. Please check them and add “.gz” string to the “Stream File” so that the gds file can be compressed. You should also add the “Technology Library” (mandatory if you are using ICFB).
  4. Click on “Show Options” button:
    a) change in "General" tab the log file name to respect the following: “topcellname.pipo”. In our example.
    b) In "Geometry" tab, check the option “Convert Half Width Path to Polygon” is activated.
  5. Finally, click on “Translate” button. You should have a popup message telling the StreamOut translation succeeded.
  6. Create a .info file, detailing technical contact and eventual data about the circuit.
  7. Send to CMP through your FTP account, the 3 required files: topcellname.gds.gz, topcellname.pipo, topcellname.info

Read more: CMP Streamout June-16.

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17. How the design can be sent ?

CMP will provide a FTP account for all the data transfer. Design transfer by email in not allowed.

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18. Is there a minimum die size ? 

Yes, the minimum charge is the price of the area indicated in the Prices page. It includes the scribe of 120µm, so the effective design surface (X x Y mm) can be calculated through the following relation: (X+0.12)*(Y+0.12)mm2 ≥ minimum area (in mm2).

19. Which steps are performed at CMP after design submission ?

The design layout has to be sent with neither seal ring, nor tiling.

CMP will process the design as follows:

IOs and standard cells from ST libraries (if any) are replaced by full layout versions
  • DRC + report to designer
  • scribe-line generation / addition of seal ring + foundry cells
  • SmartTiling and EMETRO generation
  • final DRC + report to designer
  • design is sent to ST

If DRC errors are highlighted during this process, CMP asks the designers to correct them, and the necessary steps of the flow above are again processed.

20. Any possibility of DRC derogations ?

For a correct fabrication process of the circuits, the designers have to follow strictly the DRM. If the design rules are not observed, the process could fail and the chip could not work...

However, if this cause an issue for your circuit, we can ask for you a DRC violation waiver to ST (please note this is usually difficult to be approved by ST).

For this, ST would need some slides, describing the project and detailing the importance of the waiver asked. Others information like the design area or the structure of the circuit could be appreciated.

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